The present invention relates generally to integrated circuit devices, and, more particularly, to a fast, pulse-powered NOR decode apparatus for semiconductor devices with pulse stretching and redundancy steering.
Complementary Metal Oxide Semiconductor (CMOS) technology is a popular technology not only for digital integrated circuits, but also for analog integrated circuits due to the low power dissipation, high density of integration, and low cost of fabrication properties associated therewith. CMOS includes n-type (NMOS) devices, whose source/drain current path turns on when the gate is biased more positively than the source, and p-type (PMOS) devices, which turn on when the gate is biased more negatively than the source potential. With these two complementary device types it is possible to construct logic circuits that have very low static (DC) power.
One of the problems in conventional static CMOS logic is the series connection of devices used in logic gates. For example, FIG. 1 illustrates a standard two-input CMOS static NOR gate. As is shown, the gate inputs A and B are coupled to a respective pair of series PFET transistors, as well as a pair of parallel NFET transistors. This results in a large area for static CMOS circuits, as well as a larger input capacitance. In addition, for PFET transistors, the hole mobility is about three times lower than the mobility of electrons if the transistors have comparable sizes. Accordingly, switching transients are very asymmetrical, in that the charge up transient of the capacitive load in a simple inverter (for example) takes longer than the discharge transient. To attempt to compensate, the PFET transistors are often fabricated with a large width or size to provide symmetrical switching. However, this increases the stray capacitive loads and results in an even larger area for the circuits and very inefficient area utilization. Such problems are even further exacerbated for gates having several inputs (fan-in).
An alternative logic family to static CMOS that is also often employed is what is referred to as pseudo-NMOS. An exemplary pseudo-NMOS circuit configuration of the NOR gate is shown in FIG. 2. Pseudo-NMOS technology differs from CMOS in that each input drives only a single transistor gate (i.e., each gate input is coupled to an NFET), while a PFET device has its gate grounded so as to be connected a load. This technology also has certain disadvantages, however. For a wide fan-in implementation of the pseudo-NMOS NOR circuit, as shown in FIG. 3, leakage in the NFETs of the combined parallel pull down structure can become problematic, even if the static inputs thereto are zero. Also, if a faster rise time is desired, the PFET current must be increased, which in turn raises both the power consumption and the output voltage for the zero state. Thus, although wiring complexity and device area is significantly reduced with pseudo-NMOS, static DC power consumption is increased, and noise margins are decreased.
Still another type of logic, commonly known as dynamic domino logic, offers certain advantages over static CMOS technology while retaining desirable low power dissipation characteristics. Compared to static CMOS circuits, domino logic also reduces the number of devices required to implement a particular function, leading to reduced capacitive loading and circuit size. With domino logic, a standard cell formed with a plurality of transistors represents a stage. A plurality of the stages can be cascaded or connected in series to implement the domino logic. A signal delivered to the first stage is evaluated, and the first stage produces an output signal that propagates to the second stage where the output signals of the first stage are evaluated. The second stage then produces additional output signals that, in turn, are propagated to the third stage wherein they are evaluated, and so on.
Notwithstanding the advantages offered by pseudo-NMOS logic and dynamic domino logic, in order to reduce the delay through a logic device such as an address decoder for example, a faster approach is continually sought that minimizes not only the delay from a clock, but also the setup time of the address inputs relative to the clock signal, along with the input capacitance and the power consumption.